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					Q3 2007
	Featured Highlights Download new DFT/IDFT reference design for 3G LTE systems Online DSP Builder class offers tips on using the latest version IP & Solutions New DFT/IDFT Reference Design Download Altera's new DFT/IDFT reference design to learn how you can accelerate DFT in uplink and IDFT in the downlink signal chain designs for long-term evolution (LTE) physical interfaces. This reference design meets all the specifications and requirements of the 3G LTE standard. Download the reference design to see the results for yourself. New Design Example: Cyclic Prefix Insertion for OFDM Systems How do you mitigate the effects of intersymbol interference (ISI) in OFDM systems? What are the requirements for changing system parameters on the fly, based on channel conditions and user QoS? Find the answers in this design example, which demonstrates cyclic prefix insertion for reconfigurable OFDM systems using Altera's FFT MegaCore® function. It supports run-time reconfiguration of FFT size and cyclic prefix size. Back to Top Development Boards Arria GX FPGA Development Kit When looking for excellent DSP performance for video and image processing and high-speed digital communication designs, system architects are discovering the advantages of low-cost ArriaTM GX FPGAs. See what Arria GX FPGAs can do for your DSP design with an Arria GX FPGA Development Kit. The kit delivers a complete environment for developing and testing designs that implement high-speed serial interfaces in Arria GX FPGAs. This development kit is built on a PCIe form-factor card and can be used to create designs with the PCI Express x1 and x4, Gigabit Ethernet, and Serial RapidIO® protocols. Book your kit in the eStore today! Back to Top Events & Training Online class: DSP Builder: Migrating From Version 6.1 to 7.1 In just 30 minutes, learn how to migrate older DSP Builder designs to version 7.1. Version 7.1 includes re-written blocks that make system design more efficient and intuitive. Get started today! Instructor-Led Class: Designing With Stratix III Devices December 14, Chelmsford, MA: Are you ready to take advantage of all the features in Stratix® III devices? In this one-day class, you'll learn how to use Stratix III architectural features (including enhanced DSP blocks), intellectual property, and new power innovations to build efficient Stratix III FPGA-based systems. Back to Top Literature White paper: Architecture and Component Selection for SDR Applications (PDF) Are you working in wireless communications, with a goal of developing software-defined radio (SDR)? Check out this white paper on the basics of successful SDR design. Implementing successful SDR requires positioning the digital-to-analog separation as close to the antenna as possible. When implemented with reconfigurable digital circuits, you can create an obsolescence-proof radio product that supports existing and future air-interfaces and modulation formats. See the practical requirements and how to address them in this white paper. Back to Top From the Altera Forum Running Simulations With FFT MegaCore Function Despite several hours of trying, user retokeller's simulation was not running correctly. After uploading the files to the Altera Forum, another member offered detailed suggestions and even fixed the simulation and attached it to the post! See what the problem was, and post your own tips, tricks, and suggestions today. Back to Top In the News Multimedia signal processing with programmable logic, Video/Imaging DesignLine Learn how to improve the price-to-performance ratio in multimedia devices by enabling FPGA coprocessors to do the heavy lifting. Instead of using eight to 10 DSP devices, you can replace them with one DSP device and a single FPGA. See how it's done in this how-to article. An FPGA design flow for video imaging applications, DSP DesignLine Ideal FPGA video solutions include not only IP, but also reference designs, design examples, design methodology flows, and interconnect specifications - all of which come together to enable a flexible, productive implementation for complex video applications. This article examines some of the challenges in implementing video applications in FPGAs and details how using the most advanced tools and solutions can be used to alleviate these challenges. Back to Top

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