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Your first issue of Altera's Webcast eNewsletter

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Thanks for signing up for Altera's Webcast eNewsletter. Below is the latest issue. You will usually receive this enewsletter during the first week of each month.

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Online Support Team

November 2007: Altera's monthly Webcast enewsletter provides schedules and descriptions of upcoming and recently broadcast Altera^® online seminars.

Reduce Power Consumption & Thermal Dissipation Using New Low-Cost FPGAs
Duration: 25 minutes
View Now, On Demand!

Do you want to cut power consumption in your low-cost FPGA designs? View this new webcast to learn the latest techniques in reducing power consumption and thermal dissipation.

You'll see how:

A low-cost FPGA can deliver low power consumption without
sacrificing functionality

A power-aware design flow can reduce dynamic power consumption
by 25%

To get the most accurate results from power estimation tools

You can test the latest low-cost FPGAs' power consumption yourself

Meet Your FPGA Design Requirements with Maximum Productivity
Duration: 35 minutes
View Now, On Demand!

Design engineers spend a lot of effort trying to close timing and meet power budgets. Learn how Stratix^® III FPGAs and Quartus® II software, when compared to Virtex-5 and ISE software, enable you to:

Improve performance by 25% with no degradation in performance as logic utilization increases

Save time by reducing compile times by 50%

Reduce power consumption by 45%

Lower costs with a risk-free path to structured ASICs

Drive Cost-Sensitive Automotive Applications with Low-Cost FPGAs
Duration: 15 minutes
View Now, On Demand!

Find out how Altera's low-cost FPGAs offer optimum solutions for a wide range of automotive infotainment, car networking, and driver assistance applications. You'll learn how to:

Develop a single platform for graphics processing with lower costs and greater flexibility than DSPs or other ASSP solutions

Implement all of the latest automotive networking standards, including CAN, MOST, LIN, Ethernet, and FlexRay

Differentiate your product and quickly respond to ever-changing consumer demands

The Next Industrial Revolution: Low-Cost Cyclone^® III FPGAs
Duration: 15 minutes
View Now, On Demand!

Find out how Altera's low-cost FPGAs can provide solutions for your industrial applications such as industrial Ethernet, graphics control, and embedded processing. You'll learn:

Why FPGAs are an ideal solution for industrial Ethernet applications

How Altera's newest low-cost FPGAs give you lower costs, greater flexibility, and obsolescence protection

How you can build a graphics processing human-machine interface with intellectual property, embedded processors, and FPGAs

Implementing Flexible Industrial Ethernet Solutions
Duration: 60 minutes
View Now, On Demand!

Find out how you can use low-cost FPGAs and the embedded processors to create a single flexible hardware design that can support all industrial Ethernet standards and protect you from obsolescence issues.

View webcast to learn how to:

Use low-cost FPGAs with IP-based systems to implement industrial Ethernet interfaces

Quickly modify an existing design to support a different protocol without changing the board

Find out more about Altera's solutions for industrial Ethernet

Start your industrial Ethernet design on a development board


	“I was very impressed with the [Enable High-Volume Applications with New Low-Cost FPGAs] net seminar. It was a very efficient way to learn about a new product and convenient to get immediate feedback to questions. Altera obviously has a great product with the Cyclone III FPGA. – Jon Childers, Engineer, AT Systems, Inc.

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Code:DSP enewsletter

Your first issue of Altera's Code:DSP eNewsletter

Dear Subscriber,

Thanks for signing up for Altera's Code:DSP eNewsletter. Below is the latest issue. You will receive this newsletter quarterly.

If you have any comments or suggestions about the types of information you would like to see in our newsletter, please send them to: feedback@altera.com

Thank you,
Online Support Team

Q3 2007

Featured Highlights

Download new DFT/IDFT reference design for 3G LTE systems
Online DSP Builder class offers tips on using the latest version

IP & Solutions

New DFT/IDFT Reference Design
Download Altera's new DFT/IDFT reference design to learn how you can accelerate DFT in uplink and IDFT in the downlink signal chain designs for long-term evolution (LTE) physical interfaces. This reference design meets all the specifications and requirements of the 3G LTE standard. Download the reference design to see the results for yourself.

New Design Example: Cyclic Prefix Insertion for OFDM Systems
How do you mitigate the effects of intersymbol interference (ISI) in OFDM systems? What are the requirements for changing system parameters on the fly, based on channel conditions and user QoS? Find the answers in this design example, which demonstrates cyclic prefix insertion for reconfigurable OFDM systems using Altera's FFT MegaCore^® function. It supports run-time reconfiguration of FFT size and cyclic prefix size.

Development Boards

Arria GX FPGA Development Kit
When looking for excellent DSP performance for video and image processing and high-speed digital communication designs, system architects are discovering the advantages of low-cost Arria^TM GX FPGAs. See what
Arria GX FPGAs can do for your DSP design with an Arria GX FPGA Development Kit. The kit delivers a complete environment for developing and testing designs that implement high-speed serial interfaces in Arria GX FPGAs. This development kit is built on a PCIe form-factor card and can be used to create designs with the PCI Express x1 and x4, Gigabit Ethernet, and Serial RapidIO^® protocols. Book your kit in the eStore today!

Events & Training

Online class: DSP Builder: Migrating From Version 6.1 to 7.1
In just 30 minutes, learn how to migrate older DSP Builder designs to version 7.1. Version 7.1 includes re-written blocks that make system design more efficient and intuitive. Get started today!

Instructor-Led Class: Designing With Stratix III Devices
December 14, Chelmsford, MA: Are you ready to take advantage of all the features in Stratix^® III devices? In this one-day class, you'll learn how to use Stratix III architectural features (including enhanced DSP blocks), intellectual property, and new power innovations to build efficient Stratix III FPGA-based systems.

Literature

White paper: Architecture and Component Selection for
SDR Applications (PDF)
Are you working in wireless communications, with a goal of developing software-defined radio (SDR)? Check out this white paper on the basics of successful SDR design. Implementing successful SDR requires positioning the digital-to-analog separation as close to the antenna as possible. When implemented with reconfigurable digital circuits, you can create an obsolescence-proof radio product that supports existing and future air-interfaces and modulation formats. See the practical requirements and how to address them in this white paper.

From the Altera Forum

Running Simulations With FFT MegaCore Function
Despite several hours of trying, user retokeller's simulation was not running correctly. After uploading the files to the Altera Forum, another member offered detailed suggestions and even fixed the simulation and attached it to the post! See what the problem was, and post your own tips, tricks, and suggestions today.

In the News

Multimedia signal processing with programmable logic, Video/Imaging DesignLine
Learn how to improve the price-to-performance ratio in multimedia devices by enabling FPGA coprocessors to do the heavy lifting. Instead of using eight to 10 DSP devices, you can replace them with one DSP device and a single FPGA. See how it's done in this how-to article.

An FPGA design flow for video imaging applications, DSP DesignLine
Ideal FPGA video solutions include not only IP, but also reference designs, design examples, design methodology flows, and interconnect specifications - all of which come together to enable a flexible, productive implementation for complex video applications. This article examines some of the challenges in implementing video applications in FPGAs and details how using the most advanced tools and solutions can be used to alleviate these challenges.

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